Hatem Soliman

• Senior Global Group manager of ASIC design center including disciplinary responsibilities for the team. • Responsible for the digital design activities globally for all Continental sites all over the world. • Defining strategies for technical topics, budget planning and define the milestones. • Development of the team in respect to ensure needed skills and technical capabilities for actual projects and future needs. • Coordination of resources of ASIC design centers.

• Produkt Owner, der die Einführung neuer Produkte in die Fertigung während der Tapeout-Vorbereitung, der Maskenherstellungsphase und der Fab-Vorbereitung vorantreibt • Überprüfung von PDK und FAB DRC und Abgabe von Empfehlungen für die Verletzungen für alle Technologie • Verantwortlich für den Erfolg bei der Implementierung neuer Produkte, einschließlich Design Respins/Aktualisierungen • Scrum Master und Agile Rolle für das gesamte Unternehmen Globalfoundries

•Test automation of all Intel Tapeouts. •Jobdeck/MEBES data preparation of the Mask data for different technologies. •Making automation for lapo flow and data preparation process using Perl, Python, SKILL and C++. •Kerf/Sealring verification and frame M-M XOR execution. •Experience with Eclipse, agile and CI systems like Jenkins. •Creating tools to perform layout to mask and MFDRC, Mask to Mask XORs using SVRF and TVF. •Suggest new ideas to enhance the whole layout to mask flow.

•Develop, create new features and maintenance RF/AMS EDA tools to check the layout schematic, adding layout dummies and removing old dummies automatically using skill language. • Spot the main points between technologies to move from a technology to another without any DRC errors. •Generalize the Qgen tool which used to create automatically Layout from any existing schematic of p-cells. •Automation of the Production flow and adding features to increase the flexibility and reduce the execution time.

•Technology independent implementation, maintenance and further development of several framework-integrated design flow tools based on skill programming language in/out Cadence Virtuoso Analog Design Environment. •Focus was on further development of a tool which enables easy and GUI-based import of external component models for analog simulation. This tool is generating complete Open Access (OA) Design Library database for component simulation including symbols, schematic and Verilog/Verilog-AMS.

Specialization: Leadership, Strategy and Organizational management Master thesis title: Gender Stereotypes and Perception of Leadership Competence

Master thesis title: Further-Development of a semi-automated circuit characterization Sponsor: Intel Mobile Communication Company, Munich, Germany Master thesis GPA: 1.0 Overall GPA: 1.9

Thesis title: Design, Layout, and Simulation of Uncooled Infrared Camera. GPA: Very good with honor Ranking: 15th out of 350 students (top 4%) Awards: The project ranked as number one in the graduation project competition for all Egyptian engineering universities.